Cypress Semiconductor /psoc63 /CSD0 /IDACA

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Interpret as IDACA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VAL0 (STATIC)POL_DYN 0 (VSSA_SRC)POLARITY 0 (FULL)BAL_MODE 0 (GP_STATIC)LEG1_MODE 0 (GP_STATIC)LEG2_MODE 0 (DSI_CTRL_EN)DSI_CTRL_EN 0 (IDAC_LO)RANGE 0 (LEG1_EN)LEG1_EN 0 (LEG2_EN)LEG2_EN

RANGE=IDAC_LO, LEG2_MODE=GP_STATIC, BAL_MODE=FULL, POL_DYN=STATIC, LEG1_MODE=GP_STATIC, POLARITY=VSSA_SRC

Description

IDACA Configuration

Fields

VAL

N/A

POL_DYN

N/A

0 (STATIC): N/A

1 (DYNAMIC): N/A

POLARITY

N/A

0 (VSSA_SRC): Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current.

1 (VDDA_SNK): Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current.

2 (SENSE): N/A

3 (SENSE_INV): N/A

BAL_MODE

N/A

0 (FULL): N/A

1 (PHI1): N/A

2 (PHI2): N/A

3 (PHI1_2): N/A

LEG1_MODE

N/A

0 (GP_STATIC): N/A

1 (GP): N/A

2 (CSD_STATIC): N/A

3 (CSD): N/A

LEG2_MODE

N/A

0 (GP_STATIC): N/A

1 (GP): N/A

2 (CSD_STATIC): N/A

3 (CSD): N/A

DSI_CTRL_EN

N/A

RANGE

N/A

0 (IDAC_LO): N/A

1 (IDAC_MED): N/A

2 (IDAC_HI): N/A

LEG1_EN

N/A

LEG2_EN

N/A

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